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?2015 integrated device technology, inc. 1 march 2015 dsc-4854/6 i/o control address decoder 64kx9 memory array 70v18 arbitration interrupt semaphore logic ce 0l oe l r/ w l a 15l a 0l i/o 0-8l sem l int l (2) busy l (1,2) r/ w l ce 0l oe l i/o control address decoder oe r r/ w r ce 0r a 15r a 0r i/o 0-8r sem r int r (2) r busy (1,2) m/ s (1) ce 1l r/ w r ce 0 r oe r ce 1 r 4854 drw 01 1l ce 1r ce 16 16 functional block diagram idt70v18 easily expands data bus width to 18 bits or more using the master/slave select when cascading more than one device m/ s = v ih for busy output flag on master, m/ s = v il for busy input on slave full on-chip hardware support of semaphore signaling between ports fully asynchronous operation from either port lvttl-compatible, single 3.3v (0.3v) power supply available in a 100-pin tqfp industrial temperature range (?40c to +85c) is available for selected speeds green parts available, see ordering information features true dual-ported memory cells which allow simultaneous access of the same memory location high-speed access ? commercial: 15/20ns (max.) ? industrial: 20ns (max.) low-power operation ? idt70v18l active: 440mw (typ.) standby: 660w (typ.) dual chip enables allow for depth expansion without external logic busy and interrupt flags on-chip port arbitration logic high-speed 3.3v 64k x 9 dual-port static ram idt70v18l notes: 1. busy is an input as a slave (m/ s =v il ) and an output when it is a master (m/ s =v ih ). 2. busy and int are non-tri-state totem-pole outputs (push-pull).
idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s 2 description the idt70v18 is a high-speed 64k x 9 dual-port static ram. the idt70v18 is designed to be used as a stand-alone 576k-bit dual-port ram or as a combination master/slave dual-port ram for 18-bit- or-more word system. using the idt master/slave dual-port ram approach in 18-bit or wider memory system applications results in full- speed, error-free operation without the need for additional discrete logic. this device provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature controlled by the chip enables (either ce 0 or ce 1 ) permit the on- chip circuitry of each port to enter a very low standby power mode. fabricated using cmos high-performance technology, these de- vices typically operate on only 440mw of power. the idt70v18 is packaged in a 100-pin thin quad flatpack (tqfp). notes: 1. all vcc pins must be connected to power supply. 2. all gnd pins must be connected to ground. 3. package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. pin configurations (1,2,3) index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 idt70v18pf pn100 (4 ) 100-pin tqfp top view (5 ) nc gnd gnd oe r r/ w r sem r ce 1r ce 0r nc nc gnd a 15r a 12r a 13r a 11r a 10r a 9r a 8r a 7r nc nc a 14r nc nc nc 4854 drw 02 nc nc gnd oe l r/ w l sem l ce 1l ce 0l nc nc nc vcc nc a 15l a 14l a 13l a 8l a 7l nc nc nc a 12l a 11l a 10l a 9l n c n c i / o 6 r i / o 5 r i / o 4 r i / o 3 r v c c i / o 2 r i / o 0 r g n d v c c i / o 0 l i / o 1 l g n d i / o 2 l i / o 4 l i / o 5 l i / o 6 l i / o 7 l i / o 3 l i / o 1 r i / o 7 r g n d i / o 8 l i / o 8 r n c n c a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 r i n t r b u s y r m / s b u s y l i n t l n c a 0 l g n d a 2 l a 3 l a 5 l a 6 l n c n c a 1 l a 4 l
3 idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s absolute maximum ratings (1) recommended dc operating conditions maximum operating temperature and supply voltage pin names capacitance (1) (t a = +25c, f = 1.0mhz) notes: 1. this parameter is determined by device characterization but is not produc- tion tested. 2. c out also references c i / o . n otes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 0.3v for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > vcc + 0.3v. 3. ambient temperature under bias. no ac conditions. chip deselected. notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 0.3v. notes: 1. this is the parameter t a . this is the "instant on" case temperature. symbol rating commercial & industrial unit v term (2) te r m i n a l vo l ta g e with respect to gnd -0.5 to +4.6 v t bias (3) temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperature +150 o c i out dc output current 50 ma 4854 tbl 02 grade ambient temperature (1) gnd vcc commercial 0 o c to +70 o c0v 3.3v + 0.3v industrial -40 o c to +85 o c0v 3.3v + 0.3v 48 54 tb l 03 symbol parameter conditions max. unit c in input capacitance v in = 0v 9 pf c out (2) output capacitance v out = 0v 10 pf 4854 tbl 05 left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 15l a 0r - a 15r address i/o 0l - i/o 8l i/o 0r - i/o 8r data input/output sem l sem r semaphore enable int l int r interrupt flag busy l busy r busy flag m/ s master or slave select v cc power gnd ground 4854 tbl 01 symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v gnd ground 0 0 0 v v ih input high voltage 2.0 ____ v cc +0.3 (2) v v il input low voltage -0.3 (1) ____ 0.8 v 4854 tbl 04
idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s 4 truth table iii ? semaphore read/write control (1) truth table i ? chip enable (1,2) notes: 1. chip enable references are shown above with the actual ce 0 and ce 1 levels; ce is a reference only. 2. 'h' = v ih and 'l' = v il . 3. cmos standby requires 'x' to be either < 0.2v or >v cc -0.2v. truth table ii ? non-contention read/write control notes: 1. a 0l ? a 15l a 0r ? a 15r 2. refer to chip enable truth table. notes: 1. there are eight semaphore flags written to i/o 0 and read from all the i/os (i/o 0 -i/o 8 ). these eight semaphore flags are addressed by a 0 -a 2 . 2. refer to chip enable truth table. ce ce 0 ce 1 mode l v il v ih port selected (ttl active) < 0.2v > v cc -0.2v port selected (cmos active) h v ih x port deselected (ttl inactive) xv il port deselected (ttl inactive) > v cc -0.2v x (3) port deselected (cmos inactive) x (3) < 0.2v port deselected (cmos inactive) 4 854 tbl 06 inputs (1) outputs mode ce (2) r/ w oe sem i/o 0-8 h x x h high-z deselected: power-down llxhdata in write to memory lhlhdata out read memory x x h x high-z outputs disabled 4854 tbl 07 inputs outputs mode ce (2 ) r/ w oe sem i/o 0-8 hhl ldata out read semaphore flag data out h xldata in write i/o 0 into semaphore flag lxxl ______ not allowed 4854 tbl 08
5 idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s dc electrical characteristics over the operating temperature and supply voltage range (5) (v cc = 3.3v 0.3v) notes: 1. v cc = 3.3v, t a = +25c, and are not production tested. i ccdc = 90ma (typ.) 2. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc, and using ?ac test conditions" of input levels of gnd to 3v. 3. f = 0 means no address or control lines change. 4. port "a" may be either left or right port. port "b" is the opposite from port "a". 5. refer to truth table i - chip enable. dc electrical characteristics over the operating temperature and supply voltage range (v cc = 3.3v 0.3v) notes: 1. at vcc < 2.0v, input leakages are undefined. 2. refer to truth table i - chip enable. symbol parameter test conditions 70v18l unit min. max. |i li | input leakage current (1 ) v cc = 3.6v, v in = 0v to v cc ___ 5a |i lo | output leakage current ce (2 ) = v ih , v out = 0v to v cc ___ 5a v ol output low voltage i ol = +4ma ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ v 4854 tbl 09 70v18l15 com'l only 70v18l20 com'l & ind symbol parameter test condition version typ. (1 ) max. typ. (1) max. unit i cc dynamic operating current (both ports active) ce = v il , outputs disabled sem = v ih f = f max (2) com'l l 145 235 135 205 ma ind l --- --- 135 220 i sb1 standby current (both ports - ttl level inputs) ce l = ce r = v ih sem r = sem l = v ih f = f max (2) com'l l 40 70 35 55 ma ind l --- --- 35 65 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (4 ) active port outputs disabled, f=f max (2) , sem r = sem l = v ih com'l l 100 155 90 140 ma ind l --- --- 90 150 i sb3 full standby current (both ports - all cmos level inputs) both ports ce l and ce r > v cc - 0.2v, v in > v cc - 0.2v or v in < 0.2v, f = 0 (3) sem r = sem l > v cc - 0.2v com'l l 0.2 3.0 0.2 3.0 ma ind l --- --- 0.2 3.0 i sb4 full standby current (one port - all cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (4 ) , sem r = sem l > v cc - 0.2v, v in > v cc - 0.2v or v in < 0.2v, active port outputs disabled, f = f max (2 ) com'l l 95 150 90 135 ma ind l --- --- 90 145 4854 tbl 10
idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s 6 timing of power-up power-down waveform of read cycles (5) notes: 1. timing depends on which signal is asserted last, oe or ce . 2. timing depends on which signal is de-asserted first ce or oe . 3. t bdd delay is required only in cases where the opposite port is completing a write operation to the same address location. for simu ltaneous read operations busy has no relation to valid output data. 4. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa or t bdd . 5. sem = v ih . 6. refer totruth table i - chip enable. ce (6) 4854 drw 06 t pu i cc i sb t pd 50% 50% . t rc r/ w ce (6) addr t aa oe 4854 drw 05 (4) t ace (4) t aoe (4) (1) t lz t oh (2) t hz (3,4) t bdd data out busy out valid data (4) ac test conditions figure 1. ac output load input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 3ns max. 1.5v 1.5v figures 1 and 2 4854 tbl 11 4854 drw 04 590 ? 30pf 435 ? 3.3v data out busy int 590 ? 5pf* 435 ? 3.3v data out 4854 drw 03 figure 2. output test load (for t lz , t hz , t wz , t ow ) * including scope and jig.
7 idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s 70v18l15 com'l only 70v18l20 com'l & ind unit symbol parameter min.max.min.max. read cycle t rc read cycle time 15 ____ 20 ____ ns t aa address access time ____ 15 ____ 20 ns t ace chip enable access time (3) ____ 15 ____ 20 ns t aoe output enable access time ____ 10 ____ 12 ns t oh output hold from address change 3 ____ 3 ____ ns t lz outp ut lo w-z time (1,2) 3 ____ 3 ____ ns t hz output high-z time (1,2) ____ 10 ____ 10 ns t pu chip enab le to power up time (2) 0 ____ 0 ____ ns t pd chip disable to power down time (2) ____ 15 ____ 20 ns t sop semaphore flag update pulse ( oe or sem )10 ____ 10 ____ ns t saa semaphore address access time ____ 15 ____ 20 ns 4854 tbl 12 ac electrical characteristics over the operating temperature and supply voltage range notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . either condition must be valid for the entire t ew time. 4. the specification for t dh must be met by the device supplying write data to the ram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . ac electrical characteristics over the operating temperature and supply voltage symbol parameter 70v18l15 com'l only 70v18l20 com'l & ind unit min. max. min. max. wri te cycle t wc write cycle time 15 ____ 20 ____ ns t ew chip enable to end-of-write (3) 12 ____ 15 ____ ns t aw address valid to end-of-write 12 ____ 15 ____ ns t as address set-up time (3 ) 0 ____ 0 ____ ns t wp write pulse width 12 ____ 15 ____ ns t wr write recovery time 0 ____ 0 ____ ns t dw data valid to end-of-write 10 ____ 15 ____ ns t hz output high-z time (1,2) ____ 10 ____ 10 ns t dh data hold time (4 ) 0 ____ 0 ____ ns t wz write enab le to output in high-z (1,2) ____ 10 ____ 10 ns t ow output active from end-of-write (1, 2,4) 0 ____ 0 ____ ns t swrd sem flag write to read time 5 ____ 5 ____ ns t sps sem flag contention window 5 ____ 5 ____ ns 4854 tbl 13
idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s 8 4854 drw 08 t wc t as t wr t dw t dh address data in r/ w t aw t ew (3) (2) (6) ce or sem (9,10) timing waveform of write cycle no. 1, r/ w controlled timing (1,5,8) timing waveform of write cycle no. 2, ce controlled timing (1,5) notes: 1. r/ w or ce = v ih during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a ce = v il and a r/ w = v il for memory array writing cycle. 3. t wr is measured from the earlier of ce or r/ w (or sem or r/ w ) going high to the end of write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce or sem = v il transition occurs simultaneously with or after the r/ w = v il transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce or r/ w . 7. this parameter is guaranteed by device characterization, but is not production tested. transition is measured 0mv from stead y state with the output test load (figure 2). 8. if oe = v il during r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe = v ih during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 9. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . t ew must be met for either condition. 10. refer to truth table i - chip enable . r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in ce or sem (6) (4) (4) (3) 4854 drw 07 (7) (9) (7) t lz , t hz (7)
9 idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s timing waveform of semaphore read after write timing, either side (1) notes: 1. d or = d ol = v il , ce l = ce r = v ih (refer to chip enable truth table). 2. all timing is the same for left and right ports. port "a" may be either left or right port. "b" is the opposite from port "a" . 3. this parameter is measured from r/ w "a" or sem "a" going high to r/ w "b" or sem "b" going high. 4. if t sps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be gr anted the semaphore flag. timing waveform of semaphore write contention (1,3,4) notes: 1. ce = v ih for the duration of the above timing (both write and read cycle) (refer to chip enable truth table). 2. "data out valid" represents all i/o's (i/o 0 - i/o 8 ) equal to the semaphore value. sem 4854 drw 09 t aw t ew i/o valid address t saa r/ w t wr t oh t ace valid address data valid in data out t dw t wp t dh t as t swrd t aoe read cycle write cycle a 0 -a 2 oe valid (2) t sop t sop sem "a" 4854 drw 10 t sps match r/ w "a" match a 0"a" -a 2"a" side "a" (2) sem "b" r/ w "b" a 0"b" -a 2"b" side "b" (2)
idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s 10 notes: 1. port-to-port delay through ram cells from writing port to reading port, refer to "timing waveform of write with port-to-port read and busy (m/ s = v ih )". 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of 0, t wdd ? t wp (actual), or t ddd ? t dw (actual). 4. to ensure that the write cycle is inhibited on port "b" during contention on port "a". 5. to ensure that a write cycle is completed on port "b" after contention on port "a". ac electrical characteristics over the operating temperature and supply voltage range 70v18l15 com'l only 70v18l20 com'l & ind symbol parameter min.max.min.max.unit busy timing (m/ s =v ih ) t baa busy access time from address match ____ 15 ____ 20 ns t bda busy disable time from address not matched ____ 15 ____ 20 ns t bac busy access time from chip enable low ____ 15 ____ 20 ns t bdc busy access time from chip enable high ____ 15 ____ 17 ns t aps arbitration priority set-up time (2) 5 ____ 5 ____ ns t bdd busy disable to valid data (3) ____ 15 ____ 17 ns t wh write hold after busy (5) 12 ____ 15 ____ ns busy timing (m/ s =v il ) t wb busy input to write (4) 0 ____ 0 ____ ns t wh write hold after busy (5) 12 ____ 15 ____ ns port-to-port delay timing t wdd write pulse to data delay (1 ) ____ 30 ____ 45 ns t ddd write data valid to read data delay (1) ____ 25 ____ 30 ns 4854 tbl 14
11 idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s 4854 drw 1 1 t dw t aps addr "a" t wc data out "b" match t wp r/ w "a" data in "a" addr "b" t dh valid (1) match busy "b" t bda valid t bdd t ddd (3) t wdd t baa timing waveform of write with port-to-port read and busy (m/ s = v ih ) (2,4,5) timing waveform of write with busy (m/ s = v il ) notes: 1. t wh must be met for both busy input (slave) and output (master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 3. t wb is only for the 'slave' version. notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for m/ s = v il (slave). 2. ce l = ce r = v il, refer to chip enable truth table. 3. oe = v il for the reading port. 4. if m/ s = v il (slave), busy is an input. then for this example busy "a" = v ih and busy "b" input is shown above. 5. all timing is the same for left and right ports. port "a" may be either the left or right port. port "b" is the port opposite from port "a". 4854 drw 12 r/ w "a" busy "b" t wb (3) r/ w "b" t wh (1) (2) t wp
idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s 12 ac electrical characteristics over the operating temperature and supply voltage range 70v18l15 com'l only 70v18l20 com'l & ind symbol parameter min. max. min. max. unit interrupt timing t as address set-up time 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ ns t ins interrupt set time ____ 15 ____ 20 ns t inr interrupt reset time ____ 15 ____ 20 ns 4854 tbl 15 waveform of busy arbitration controlled by ce timing (m/ s = v ih ) (1,3) waveform of busy arbitration cycle controlled by address match timing (m/ s = v ih ) (1) notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from port ?a?. 2. if t aps is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. 3. refer to truth table i - chip enable. 4854 drw 13 addr "a" and "b" addresses match ce "a" ce "b" busy "b" t aps t bac t bdc (2) 4854 drw 14 addr "a" address "n" addr "b" busy "b" t aps t baa t bda (2) matching address "n"
13 idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s truth table iv ? interrupt flag (1,4,5) waveform of interrupt timing (1,5) notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from port ?a?. 2. refer to interrupt truth table. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. 5. refer to truth table i - chip enable. notes: 1. assumes busy l = busy r =v ih . 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. int l and int r must be initialized at power-up. 5. refer to truth table i - chip enable. 4854 drw 15 addr "a" interrupt set address ce "a" r/ w "a" t as t wc t wr (3) (4) t ins (3) int "b" (2) 4854 drw 16 addr "b" interrupt clear address ce "b" oe "b" t as t rc (3) t inr (3) int "b" (2) left port right port function r/ w l ce l oe l a 15l -a 0l int l r/ w r ce r oe r a 15r -a 0r int r l l x ffff x x x x x l (2) set right int r flag xxxxxxllffffh (3) reset right int r flag xxx x l (3) l l x fffe x set left int l flag x l l fffe h (2 ) x x x x x reset left int l flag 4854 tbl 16
idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s 14 functional description the idt70v18 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt70v18 has an automatic power down feature controlled by ce . the ce 0 and ce 1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce = v ih ). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location fffe (hex), where a write is defined as ce r = r/ w r = v il per the truth table. the left port clears the interrupt through access of address location fffe when ce l = oe l = v il , r/ w is a "don't care". likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location ffff (hex) and to clear the interrupt flag ( int r ), the right port must read the memory location ffff. the message (9 bits) at fffe or ffff is user-defined since it is an addressable sram location. if the interrupt function is not used, address locations fffe and ffff are not used as mail boxes, but as part of the random access memory. refer to truth table iv for the interrupt operation. truth table v ? address busy arbitration (4) notes: 1. pins busy l and busy r are both outputs when the part is configured as a master. both are inputs when configured as a slave. busy outputs on the idt70v18 are push- pull, not open drain outputs. on slaves the busy input internally inhibits writes. 2. "l" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "h" if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs can not be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. 4. refer to truth table i - chip enable. truth table vi ? example of semaphore procurement sequence (1,2,3) notes: 1. this table denotes a sequence of events for only one of the eight semaphores on the idt70v18. 2. there are eight semaphore flags written to via i/o 0 and read from all i/o's (i/o 0 -i/o 8 ). these eight semaphores are addressed by a 0 - a 2 . 3. ce = v ih , sem = v il to access the semaphores. refer to truth table iii - semaphore read/write control. inputs outputs function ce l ce r a ol -a 15l a or -a 15r busy l (1) busy r (1) x x no match h h normal h x match h h normal x h match h h normal l l match (2) (2) write inhibit (3 ) 4854 tbl 17 functions d 0 - d 8 left d 0 - d 8 right status no action 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token right port writes "0" to semaphore 0 1 no change. right side has no write access to semaphore left port writes "1" to semaphore 1 0 right port obtains semaphore token left port writes "0" to semaphore 1 0 no change. left port has no write access to semaphore right port writes "1" to semaphore 0 1 left port obtains semaphore token left port writes "1" to semaphore 1 1 semaphore free right port writes "0" to semaphore 1 0 right port has semaphore token right port writes "1" to semaphore 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token left port writes "1" to semaphore 1 1 semaphore free 4854 tbl 18
15 idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s busy logic busy logic provides a hardware indication that both ports of the ram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the ram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applica- tions. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. if the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the m/ s pin. once in slave mode the busy pin operates solely as a write inhibit input pin. normal operation can be programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. the busy outputs on the idt70v18 ram in master mode, are push-pull type outputs and do not require pull up resistors to operate. if these rams are being expanded in depth, then the busy indication for the resulting array requires the use of an external and gate. address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with the r/ w signal. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. semaphores the idt70v18 is an extremely fast dual-port 64k x 9 cmos static ram with an additional 8 address locations dedicated to binary semaphore flags. these flags allow either processor on the left or right side of the dual-port ram to claim a privilege over the other processor for functions defined by the system designer?s software. as an ex- ample, the semaphore can be used by one processor to inhibit the other from accessing a portion of the dual-port ram or any other shared resource. the dual-port ram features a fast access time, with both ports being completely independent of each other. this means that the activity on the left port in no way slows the access time of the right port. both ports are identical in function to standard cmos static ram and can be read from or written to at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous read/write of, a non-semaphore location. semaphores are pro- tected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the dual-port ram. these devices have an automatic power-down feature controlled by ce , the dual-port ram enable, and sem , the semaphore enable. the ce and sem pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. this is the condition which is shown in truth table iii where ce and sem are both high. systems which can best use the idt70v18 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. these systems can benefit from a performance increase offered by the idt70v18s hardware semaphores, which provide a lockout mechanism without requiring complex programming. software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. the idt70v18 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. an advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. this can prove to be a major advantage in very high-speed systems. how the semaphore flags work the semaphore logic is a set of eight latches which are indepen- dent of the dual-port ram. these latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphores provide a hardware assist for a use assignment method called ?token passing allocation.? in this method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. if the left processor wants to use this resource, it requests the token by setting the latch. this processor then width expansion with busy logic master/slave arrays when expanding an idt70v18 ram array in width while using busy logic, one master part is used to decide which side of the rams array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master use the busy signal as a write inhibit signal. thus on the idt70v18 ram the busy pin is an output if the part is used as a master (m/ s pin = v ih ), and the busy pin is an input if the part used as a slave (m/ s pin = v il ) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. the busy arbitration on a master is based on the chip enable and figure 3. busy and chip enable routing for both width and depth expansion with idt70v18 rams. 4854 drw 17 master dual port ram busy r ce 0 master dual port ram busy r slave dual port ram busy r slave dual port ram busy r ce 1 ce 1 ce 0 a 16 busy l busy l busy l busy l .
idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s 16 d 4854 drw 18 0 d q write d 0 d q write semaphore request flip flop semaphore request flip flop lport rport semaphore read semaphore read verifies its success in setting the latch by reading it. if it was successful, it proceeds to assume control over the shared resource. if it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. the left processor can then either repeatedly request that semaphore?s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. once the right side has relinquished the token, the left side should succeed in gaining control. the semaphore flags are active low. a token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. the eight semaphore flags reside within the idt70v18 in a separate memory space from the dual-port ram. this address space is accessed by placing a low input on the sem pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, ce , and r/ w ) as they would be used in accessing a standard static ram. each of the flags has a unique address which can be accessed by either side through address pins a 0 ? a 2 . when accessing the semaphores, none of the other address pins has any effect. when writing to a semaphore, only data pin d 0 is used. if a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see truth table vi). that semaphore can now only be modified by the side showing the zero. when a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. the fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (a thor- ough discussion on the use of this feature follows shortly.) a zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. when a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. the read value is latched into one side?s output register when that side's semaphore select ( sem ) and output enable ( oe ) signals go active. this serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. because of this latch, a repeated read of a semaphore in a test loop must cause either signal ( sem or oe ) to go inactive or the output will never change. a sequence write/read must be used by the semaphore in order to guarantee that no system level contention will occur. a processor requests access to shared resources by attempting to write a zero into a semaphore location. if the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see table vi). as an example, assume a processor writes a zero to the left port at a free semaphore location. on a subsequent read, the processor will verify that it has written success- fully to that location and will assume control over the resource in question. meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. had a sequence of read/write been used instead, system contention problems could have occurred during the gap between the read and write cycles. it is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. the reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in figure 4. two sema- phore request latches feed into a semaphore flag. whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. this condition will continue until a one is written to the same semaphore request latch. should the other side?s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side?s request latch. the second side?s flag will now stay low until its semaphore request latch is written to a one. from this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. the critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. the semaphore logic is specially designed to resolve this problem. if simultaneous requests are made, the logic guarantees that only one side receives the token. if one side is earlier than the other in making the request, the first side to make the request will receive the token. if both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. one caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. as with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. since any sema- phore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. figure 4. idt70v18 semaphore logic
17 idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s ordering information 4854 drw 19 pf 100-pin tqfp (pn100) 15 20 speed in nanoseconds commercial only commercial & industrial l low power 576k (64k x 9) 3.3v dual-port ram 70v18 a power 999 speed a package xxxxx device type a process/ temperature range blank i commercial (0c to +70c) industrial (-40c to +85c) blank 8 tube or tray tape and reel g green a a (1) (2) datasheet document history: 09/30/99: initial public offering 11/10/99: page 1 & 17 replaced idt logo 04/10/00: page 2 fixed incorrect pin number 01/02/02: page 3 increased storage temperature parameter clarified t a parameter page 4 fixed i/o 8 in notes page 5 dc electrical parameters?changed wording from "open" to "disabled" added truth table i - chip enable as note 5 page 6 fixed 5pf* in drawing 04 page 7 corrected 200mv to 0mv in notes pages 5, 7, 10 & 12 added industrial temperature range for 20ns to dc & ac electrical characteristics page 3, 5, 7, 10 & 12 removed industrial temp option footnote from all tables page 1 & 17 replace idt tm logo with idt ? logo 10/21/04: removed preliminary status page 4 added junction temp to the absolute maximum ratings table updated capacitance table page 8 updated timing waveform of write cycle no. 1, r/ w controlled timing page 1 & 17 replaced old idt ? logo with new idt tm logo 01/29/09: page 17 removed "idt" from orderable part number 1. industrial temperature range is available. for specific speeds, packages and powers contact your sales office. 2. green parts available. for specific speeds, packages and powers contact your local sales office.
idt70v18l high-speed 3.3v 64k x 9 dual-port static ram industrial and commercial temperature range s 18 datasheet document history (con't.) 03/19/15:: page 1 added green availability to features page 17 added green indicator with footnote to ordering information page 2 removed idt in reference to fabrication page 2 &17 the package code pn100-1 changed to pn100 to match standard package codes page 17 added tape and reel to ordering information page 17 added footnote to industrial temp indicating availability the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com

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